1. Technical Field
Embodiments of the present disclosure may generally relate to a repair device and a semiconductor device including the same, and more particularly to a technology for storing failure information in a fuse circuit during a test operation.
2. Background Art
A semiconductor memory device is constructed of a plurality of memory cells which are arranged in the form of a matrix. However, if a defective or failed cell occurs in at least one memory cell from among a plurality of memory cells, it is impossible for a semiconductor memory device to normally operate, so that the semiconductor memory device having the defective cell is regarded as a defective product and abandoned. As the semiconductor memory device has been developed to have a higher degree of integration at a higher speed, there is a higher possibility of causing defective cells. Provided that the entirety of the semiconductor memory device is discarded due to a defect generated in only a few memory cells among all memory cells contained in the semiconductor memory device, the discarding of the entirety of the semiconductor memory device is cost ineffective and is far from high product efficiency.
As a result, a production yield denoted by the ratio of a total number of produced chips to the number of normal chips, which is needed for deciding production costs of semiconductor memory devices, is gradually reduced. Therefore, in order to increase a production yield of semiconductor memory devices, many developers and companies are conducting intensive research into a method for constructing highly-integrated semiconductor memory devices configured to operate at a higher speed and a method for efficiently repairing defective cells.
As an exemplary method for repairing the defective cell, a technology for embedding a repair circuit configured to replace a defective cell with a redundancy cell, into the semiconductor memory device has been widely used. Generally, the repair circuit includes redundancy columns/rows in which redundancy memory cells are arranged in rows and columns.
The repair circuit selects the redundancy column/row to substitute for the defective column/row. That is, if a row and/or column address signal for designating a defective cell is input to the repair circuit, the repair circuit selects the redundancy column/row instead of the defective column/row of a memory cell bank.
In order to recognize an address for designating a defective cell, the semiconductor memory device includes a plurality of fuses capable of being blown, and the fuses are selectively blown so that an address of the defective cell can be programmed.